This paper reports on nanoscale electrical investigations on some dielectrics that can be adopted to optimize the performances of SiC and GaN transistors. In particular, in the case of SiC the discussion is focused on the optimization of SiO 2 /SiC interfaces in 4H-SiC MOSFETs technology with particular attention to the active doping incorporation during the post oxide deposition thermal processes. On the other hand, the origin of a Poole-Frenkel (PF) emission through the insulator layer in NiO/AlGaN/GaN diodes was found employing a high later resolution investigation by conductive atomic force microscopy that revealed preferential conduction spots not related to dielectric breakdown events.