Engineering of the tunnel barrier of non-volatile memories is addressed in this paper. The strong potential of multilayer stacks for reducing the programming times of these devices, without altering their retention characteristics, is studied. To this aim, experimental results showing the improved field sensitivity of the gate current of MOS devices with SiO 2/HfO 2 gate stacks compared to SiO 2 of identical electrical thickness (EOT) are presented. Simulations of the corresponding tunnelling currents are also reported. Our electrical measurements suggest that it is of great interest to investigate the use of SiO 2/HfO 2 stacks as tunnel barriers for NVMs. These experimental results on double-layer stacks allow to confirm experimentally a conduction principal that could be used in symmetrical triple-layer SiO 2/high-k/SiO 2 tunnel barriers, thus allowing an advantageous behaviour in both conduction directions. Further …