Silicon nanocrystal (Si-nc) trapping layers offer several advantages on standard poly-Si floating gates, as improved data retention after endurance in particular at high temperatures, robustness toward oxide defects, two-bits per cell storage and full compatibility toward CMOS process. It has also been shown that coupling the Si-nc concept with high-k control dielectrics, by improving the gate coupling ratio, enables Fowler-Nordheim (FN) program/erase. However, one of the key limitations of Si-nc memories is the limited memory window which is not suitable for multi-level memory applications. The use of two stacked Si-ncs layers to increase the number of trapping sites has been previously discussed in the literature with a SiO 2 control oxide. In this work, we present memory devices with double stacked Si-nc layers and high-k (HfAlO-based) control dielectrics. We also propose to cover the 2 nd Si-nc layer with a thin …