We investigated the feasibility of electron programing and hole erasing in silicon nanocrystal Flash memory cells with fin field-effect transistor architecture having ultrashort channels (90nm). Experiments show that, by choosing a proper program/erase condition, very large threshold voltage windows can be achieved, compatible with the needs of multilevel cells. These performances are coupled to excellent retention at high temperature. The obtained results evidence that hole trapping is less affected by electric field and temperature stress compared to electron trapping. Qualitative explanations for this behavior are given.
American Institute of Physics
19 May 2008
Volume: 92 Issue: 20 Pages: 203503
Applied Physics Letters