In this letter, SiO2 layers deposited on 4H-SiC and subjected to different post deposition annealing (PDA) in NO and N2O served as case study to identify the key factors influencing the channel mobility and threshold voltage stability in 4H-SiC MOSFETs. In particular, PDA in NO gave a higher channel mobility (55 cm2V-1s-1) than PDA in N2O (20 cm2V-1s-1), and the subthreshold behavior of the devices confirmed a lower total amount of interface states for the NO case. Cyclic gate bias stress measurements allowed to separate the contributions of interface states (Nit) and near interface oxide traps (NIOTs) in the two oxides. In particular, it was found that NO annealing reduced the total density of charge trapped down to 3 x 1011 cm-2 at the interface states and to 1 x 1011 cm-2 inside the oxide. Electron energy loss spectroscopy demonstrated that the reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide (~ 1nm) and carbon-related defects (< 1nm) at the interface, respectively. This correlation explained the mobility and threshold voltage behavior of 4H-SiC MOSFETs.