Modern semiconductor heterostructures can contain multiple populations of distinct carrier species which can be: intentional (e.g., p-n junctions), arising naturally due to carriers in more than one eigenenergy state (e.g., inversion/accumulation layers and quantum wells), or unintentional due to parasitic conduction channels (e.g., conduction through barrier and/or channel/substrate in heterostructure field-effect transistors). Accurate characterisation of electronic transport properties in such structures demands a more sophisticated methodology than the conventional analysis of Hall-effect measurements at a single value of magnetic field intensity. Even though multi-carrier fitting (MCF) can be employed to analyse magnetic field dependent Hall and resistivity data, this approach does not yield unique transport parameters because it demands starting assumptions regarding the number and type of carriers present, as well as initial estimates for the corresponding mobilities and densities. This difficulty can be overcome by using the mobility spectrum analysis technique (first proposed by Beck and Anderson in 1987 [1] which, over the last decades, has evolved into a sophisticated methodology with numerous implementations, including the commercially available quantitative mobility spectrum analysis (QMSA)[2], maximum-entropy mobility spectrum analysis (MEMSA) [3], and the high-resolution mobility spectrum analysis (HRMSA)[4]. In this work, we present results of mobility spectrum analysis-based studies of electronic transport in wide bangap semiconductor structures, including SiC-based MOSFETs and GaN-based high electron mobility field effect transistor (HEMT) structures. It is shown that the MSA approach can provide information that aids optimisation of the epitaxial growth and device fabrication processes, and can also yield greater insight into the fundamental scattering mechanisms and electronic transport phenomena in two-dimensional inversion and accumulation layers. Figure 1 shows the mobility peaks associated with interface and bulk electron populations in SiC-based MOSFET with an ion-implanted buried n-type layer at a gate bias of 15 V [5].
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5. G. A. Umana-Membreno et al, Microelec. Eng. 147, 137 (2015)