In this paper nanocrystals memories program curves are shown and their saturation points (steady state condition) can be observed. We present a model that relates the voltage shift at the steady state (Δ V T ss) to the gate program voltage (V G). Starting from a good agreement between experimental data and simulations for nanocrystals memory cells with a conventional dielectric structure (SiO 2), we present the estimated values of the Δ V T ss vs V G for different control stacks. Our investigation shows an improvement if a material with a high dielectric constant and a small conduction band-offset with respect to the SiO 2, is placed between two SiO 2 layers when the first of them is very thin.